1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device for reading out data in response to a control clock signal and an address signal applied externally.
2. Description of the Background Art
FIG. 8 is a timing chart illustrating consecutive readout operations of a conventional dynamic random access memory (hereinafter referred to as a DRAM). Such a DRAM is disclosed in, for example, U.S. Pat. No. 4,649,522.
Referring to FIG. 8, a row address ROW is taken in when a signal /RAS falls at time t0, and a first column address COL1 is taken in when a signal /CAS (control clock signal) falls at time t1. After a column access time period t.sub.CA has passed from time t1, data D1 at an address specified by row address ROW and column address COL1 is output. Output of data D1 continues even after the subsequent rise of signal /CAS at time t2 and is stopped after a data hold time period t.sub.DH has passed from the fall of signal /CAS at time t3. Here, the relationship t.sub.DH &lt;t.sub.CA holds true.
A second column address COL2 is taken in when signal /CAS falls at time t3, and data D2 addressed by row address ROW and column address COL2 is output after column access time period t.sub.CA has passed from time t3.
Thus, in such a DRAM, output of data continues for an "H" (High) level period of signal /CAS in addition to an "L" (Low) level period thereof in order to achieve a high-speed column access.
The DRAM described above, however, gives rise to the following problem. Let us consider an example in which a computer with two banks A and B is constructed by using two of such DRAMs to perform interleave operations. Here, it is assumed that interleave operations are the operations in which two banks A and B are alternately accessed so that column access time period t.sub.CA appears to be non-existent.
FIG. 9 is a timing chart illustrating the interleave operations of such a computer. Here, signals /CAS-A and /CAS-B are the signals /CAS for banks A and B, respectively, and data DQ-A and DQ-B are the data DQ for banks A and B, respectively.
Referring to FIG. 9, data DA1 corresponding to a fall of signal /CAS-A at time t0 is output after column access time period t.sub.CA has elapsed from time t0. Data DB1 corresponding to a fall of signal /CAS-B at time t1 is output after column access time period t.sub.CA has elapsed from time t1. When signal /CAS-A falls again at time t2, output of data DA1 in bank A is stopped after data hold time period t.sub.DH has elapsed from time t2, and the next data DA2 in bank A is output after column access time period t.sub.CA has elapsed from time t2.
During data hold time period t.sub.DH starting from time t2, data is output from both of the two banks A and B, whereby collision of data occurs. As a result, data cannot be taken in correctly at the falling edge or the rising edge of signal /CAS.